GE IS200ERIOH1AAA Exciter‑Regulator I/O Board (ERIO)

IS200ERIOH1AAA (ERIO board) is core regulator I/O interface board for GE Mark VI Speedtronic and EX2100 generator excitation system. It is installed in ERBP / ERRB exciter back‑plane rack, serves as signal bridge between DSPX controller board, field terminal boards (EPCT, ECTBG2) and other internal functional boards such as ERDD, EROC. It conditions generator PT/CT voltage‑current sampling signals, discrete interlock signals, excitation sequence and protection I/O signals. Conformal‑coated PCB adapts to heavy‑duty power‑plant environment, supports both simplex and TMR triple‑modular‑redundant excitation architectures. It exchanges real‑time I/O data with DSPX via VME back‑plane bus, and provides front‑panel test port for on‑site commissioning and fault diagnosis。Product status: Obsolete, spare‑part only supply available。

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Description

Hardware & Electrical Specifications

  • Model:IS200ERIOH1AAA
  • Part Number:IS200ERIOH1AAA
  • Module Type:Exciter‑Regulator I/O Board (ERIO)
  • Form factor:Single‑slot double‑height 6U VME plug‑in board
  • Power supply:+5 V DC from exciter backplane, typical power consumption 10 W
  • Backplane interface:Dual 96‑pin P1/P2 VME back‑plane connectors
  • Front‑panel connectors:2‑pcs 25‑pin D‑Sub (connect to EPCT / ECTBG2 terminal boards); 9‑pin TEST diagnostic port
  • Signal processing:Condition PT/CT analog sampling, digital interlock & protection I/O for excitation loop
  • Isolation:Channel‑to‑backplane galvanic isolation, 1500 V DC isolation rating
  • Scan rate:Typical 5 ms signal update for AVR closed‑loop control
  • PCB treatment:Conformal coated for dust‑moisture‑corrosion resistance
  • On‑board protection:ESD protection, surge suppression, hardware watchdog circuit
  • Compatibility note:Cannot run standalone; must match EX2100 system hardware revision; simplex fits ERBP rack; redundant system installs on ERRB rack; full‑signal‑loop test required after replacement。

Environmental Specifications

  • Operating temperature:‑40 ℃ ~ +70 ℃
  • Storage temperature:‑40 ℃ ~ +85 ℃
  • Relative humidity:5%‑95% non‑condensing
  • Installation location:Excitation control cabinet ERBP / ERRB rack
  • EMC compliance:IEC 61000‑6‑2
  • Certifications:CE

Mechanical Data

  • Weight:approx 1.0 kg
  • Dimension:340 mm × 216 mm × 55 mm
  • Handling note:ESD‑sensitive PCB, anti‑static wrist‑strap mandatory during handling
  • Recommended wire cross‑section:0.75‑2.5 mm² shielded twisted‑pair copper cable for D‑Sub interconnection cables
  • Terminal tightening torque:0.6‑1.0 N·m

Main Functions

  1. Condition and route PT/CT generator voltage & current sampling signals from EPCT terminal board to DSPX controller for AVR regulation calculation。
  2. Receive external discrete interlock signals (breaker status, permit‑to‑run, trip commands) from ECTBG2 terminal board.
  3. Interface internal system I/O signals to ERDD dynamic‑discharge board and EROC option board.
  4. Route excitation control output, trip‑logic and alarm signals between back‑plane bus and field‑side terminal assemblies.
  5. Front‑panel TEST port supports real‑time signal monitoring for commissioning and troubleshooting.
  6. On‑board hardware self‑diagnosis: detect power failure, signal‑chain abnormality, VME‑bus communication loss, report fault status to main controller.
  7. Front‑panel LED status indication:
    • Green LED:Board power supply normal
    • Yellow LED:VME‑bus communication active
    • Red LED:Signal‑chain fault / hardware failure

Installation & Wiring Requirements

  1. Cut off excitation rack power supply before replacement. Hot‑swap is forbidden. Strict anti‑static protection when handling PCB board.
  2. Insert module fully into designated ERBP / ERRB rack slot, lock ejector levers to guarantee reliable back‑plane contact.
  3. Connect front‑panel D‑Sub cables to EPCT / ECTBG2 terminal boards strictly follow GE EX2100 wiring manual; separate weak‑signal cables from high‑power cables.
  4. Complete protective grounding according to GE Speedtronic system specification.
  5. After replacement: verify VME‑bus link status, check PT/CT sampling value, validate interlock‑signal response, perform full excitation‑loop static test before commissioning.
  6. Replacement note: Confirm hardware revision matches system simplex/redundant architecture; full‑function signal‑loop test is mandatory after swap.

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