GE IS210AEDBH4AGD AEDB AE Discrete Bridge I/O Pack

Description

Hardware & Electrical Specifications

• Model：IS210AEDBH4AGD
• Part Number：IS210AEDBH4AGD
• Module Type：AEDB AE Discrete Bridge I/O Pack
• Mounting：Standard Mark VIe I/O‑pack rack, communicate via dual redundant IONet field‑bus
• Power supply：24 VDC rack backplane auxiliary power; typical power consumption ＜14 W
• Discrete input：Multi‑channel galvanic‑isolated wet/dry contact input; configurable debounce filter for limit‑switch, permissive and fault feedback signals
• Discrete output：Solid‑state isolated discrete output channels for driving auxiliary relays, contactors and interlock solenoid circuits
• Auxiliary bridge interface：Auxiliary signal conditioning circuit for auxiliary bridge‑transducer signals inside excitation cabinet
• Channel isolation：Enhanced high‑voltage galvanic channel‑to‑channel isolation for heavy industrial noise environment
• Communication：Dual‑port redundant IONet high‑speed serial communication interface
• PCB treatment：AGD‑revision enhanced conformal coated for dust‑moisture‑corrosion resistance, improved ESD and surge immunity
• On‑board protection：ESD protection, MOV surge suppression, input over‑voltage limiting, output short‑circuit protection, contact‑fault diagnosis, watchdog self‑monitor circuit, dual‑IONet link‑failure detection
• Compatibility note：Cannot run standalone; must match Mark VIe / EX2100e controller and corresponding field terminal assemblies; full discrete‑loop simulation test mandatory after replacement.

Environmental Specifications

• Operating temperature：‑20 ℃ ~ +65 ℃
• Storage temperature：‑40 ℃ ~ +85 ℃
• Relative humidity：5%‑95% non‑condensing
• Installation location：Indoor turbine control cabinet / excitation cabinet
• EMC compliance：IEC 61000‑6‑2
• Certifications：CE

Mechanical Data

• Weight：approx 0.39 kg
• Dimension：Standard Mark VIe I/O pack form‑factor
• Handling note：ESD‑sensitive PCB; mixed discrete‑signal and weak‑signal conditioning circuit, anti‑static wrist‑strap mandatory during handling
• Terminal tightening torque：0.6‑1.0 N·m

Main Functions

1. Collect multi‑channel discrete contact status signals from field limit switches, permissive contacts and equipment‑fault feedback. Configurable software debounce filter suppresses contact bounce interference.
2. Output isolated solid‑state drive signals to actuate auxiliary relays, contactors and interlock solenoid valves for turbine startup sequence, auxiliary equipment enable‑disable logic.
3. Provide auxiliary bridge‑signal conditioning for minor transducer signals inside generator excitation cabinet.
4. Transmit discrete status data and receive output commands from Mark VIe / EX2100e main controller via dual redundant IONet bus.
5. On‑board channel‑level self‑diagnosis: detect input signal anomaly, output over‑current / short‑circuit, watchdog timeout and dual‑IONet communication link failure; upload fault alarm to turbine main controller.
6. LED status indication:
   • Green LED：Module power supply normal / RUN status
   • Yellow LED：IONet bus communication active
   • Red LED：I/O‑channel fault / module FAIL alarm

Installation & Wiring Requirements

1. Cut off rack power supply before replacement. Hot‑swap is forbidden for non‑hot‑swap configuration; strictly follow Mark VIe maintenance procedure for hot‑swap version. Strict anti‑static protection when handling PCB board.
2. Insert I/O pack into designated rack slot, engage locking mechanism; ensure backplane connection is reliable.
3. Field discrete‑signal wiring strictly follow GE Speedtronic Mark VIe wiring manual; signal cables adopt shielded twisted‑pair, strictly separated from high‑power cables; connect shielding to dedicated ground terminal.
4. Complete protective grounding according to GE system specification.
5. After replacement: verify module power‑on status, check each‑channel discrete reading, simulate input‑contact fault and output‑drive test before commissioning.
6. Replacement note: For TMR triple‑redundant system application, hardware consistency of related redundant packs shall be verified; full discrete‑loop simulation test mandatory after unit put‑into‑service.